December 2026 batchCall for applications
6-Month VLSI Design & Tape-out Internship
A hands-on internship for B.Tech students: learn the complete chip-design flow, build a capstone design of your own and take it to a tape-out-ready layout.
- Track ADigital VLSI DesignRTL-to-GDSII
- Track BAnalog & Mixed-Signal DesignSpecification to GDSII
- 6 months26 weeks, about 17 hours per week
- ₹50,000programme fee + applicable taxes
- Real siliconoptional VACS tape-out on GF180MCU or UMC65
Important dates
- Last date to apply25 Nov 2026
- Selection results30 Nov 2026
- Internship begins10 Dec 2026
Trusted by Innovators and Institutions
Government
Universities
Research Labs
Startups
MSMEs
Supporting India's Semiconductor Mission Aligned with MeitY initiatives, including the SMDP-C2S programme.
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AI Hardware
Custom AI Accelerators
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LWE · TRNG · FHE
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Built by researchers, for innovators.
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Making ASIC fabrication accessible.
Commercial + Open Source EDA
Cadence, Synopsys, OpenROAD, OpenLane, Yosys, Magic & more.
End-to-End Excellence
From architecture to silicon.
Made for India
Proudly supporting Atmanirbhar Bharat.
UMC65 · GF22 · GF180MCU
Technology Nodes
MPW Tapeout
Support
Open Source EDA Flow
Supported
End-to-End Silicon Enablement
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